The present application relates to semiconductor device fabrication, and more particularly, to methods and structures for preventing contact shorts in a one-sided gate tie-down structure.
An integrated circuit fabricated on a semiconductor substrate typically requires metal interconnects for electrically interconnecting discrete semiconductor devices on the semiconductor substrate. At 7 nm node, a one-sided gate tie-down structure having a shared contact may be employed to electrically connect a gate conductor of a gate structure to a source/drain contact located at one side of the gate structure (i.e., target source/drain contact). However, as the transistor dimensions shrink, it is increasingly difficult to maintain precise overlay tolerance, with the result that even small misalignments of the masks in the formation of contact openings within which the shared contact forms will result in the exposure of a small portion or “border” of another source/drain contact located at an opposite side of the gate structure. As a result, the shared contact may connect not only the gate conductor and the target source/drain contact, but also the undesired another source/drain contact, causing contact shorts. Therefore, there remains a need for a structure that can effectively prevent electrical shorts a one-sided gate tie-down structure for 7 nm node and beyond.